Let us return to the model of a two-input multiplexer in Example 5.4. So the half_add process above could be rewritten asĮxample 5.6 A revised model of a two- input multiplexer A process with a sensitivity list in its heading is exactly equivalent to a process with a wait statement at the end, containing a sensitivity clause naming the signals in the sensitivity list. This form of process is so common in modeling digital systems that VHDL provides the shorthand notation that we have seen in many examples in preceding chapters.
When that happens, the process resumes and starts execution from the top. The process starts execution by generating values for sum and carry based on the initial values of a and b, then suspends on the wait statement until either a or b (or both) change values. This style of wait statement is useful in a process that models a block of combinatorial logic, since any change on the inputs may result in new output values for example: If we just include a sensitivity clause in a wait statement, the process will resume whenever any one of the listed signals changes value, that is, whenever an event occurs on any of the signals. The sensitivity clause, starting with the word on, allows us to specify a list of signals to which the process responds. Let us go through each clause and describe what it specifies. We can include any combination of these clauses, or we may omit all three. The sensitivity clause, condition clause and timeout clause specify when the process is subsequently to resume execution.
The purpose of the wait statement is to cause the process that executes the statement to suspend execution. We will discuss labeled statements in Chapter 20. The optional label allows us to identify the statement. A wait statement is a sequential statement with the following syntax rule:
#Multiplexer 4 a 1 vhdl how to#
Now that we have seen how to change the values of signals over time, the next step in behavioral modeling is to specify when processes respond to changes in signal values. Ashenden, in The Designer's Guide to VHDL (Third Edition), 2008 5.2.3 Wait Statements
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